This application claims benefit of priority under 35 USC xc2xa7119 to Japanese Patent Application No. 2000-89702, filed on Mar. 28, 2000, the contents of which are incorporated by reference herein.
1. Field of the Invention
The present invention relates generally to a semiconductor memory device.
2. Description of Related Art
Generally, in the design for semiconductor memory devices such as SRAMs (Static Random Access Memories), products, which have different bit configurations even if their storage capacities are the same, are designed at the same time at a customer""s request. For example, with respect to an SRAM having a storage capacity of 9 Mbits, its bit configurations including redundant divisions are various configurations, such as 256 kwordsxc3x9736 bits or 512 kwordsxc3x9718 bits, in accordance with its uses.
Usually, such products having different bit configurations are realized by changing a wiring layer by switching a mask for a specific in the same chip.
The layout of a memory cell array of a typical SRAM is shown in FIG. 4. In this SRAM, a memory cell array is divided into two cell arrays Ar1 and Ar2 on a chip. Each of the cell arrays Ari (i=1, 2) comprises k section parts S1, . . . , Sk. Each of the section parts Si (i=1, . . . , k) of the cell array Ar1 has n input/output part I/O1, . . . , I/On, and each of the section parts Sj (j=1, . . . , k) of the cell array Ar2 has n input/output parts I/On+1, . . . , I/O2n.
The construction of a conventional semiconductor memory device having the layout of the memory cell shown in FIG. 4 is shown in FIG. 5. In this conventional semiconductor memory device, the n input/output parts I/O1, . . . , I/On of each of the section parts Si (i=1, . . . , k) of the cell array Ar1 are connected to one ends of first through n-th output signal lines, and the n input/output parts I/O1, . . , I/On of each of the section parts Sj (j=1, . . . , k) of the cell array Ar2 are connected to one ends of (n+1)-th through 2n-th output signal lines. That is, the j-th (j=1, . . . , n) input/output part I/Oj of the section part Si (i=1, . . . , k) of the cell array Ar1 is connected to one end of the j-th output signal line, and the j-th (j=1, . . . , k) input/output part I/O of the section part Si (i=1, . . . , k) of the cell array Ar2 is connected to one end of the (n+j)-th output signal line.
The above described semiconductor memory device also has 2n output control circuits 31, . . . , 32n, and 2n output transistor circuits (which will be also hereinafter referred to as output Tr circuits) 51, . . . , 52n. The other end of the i-th (i=1, . . . , 2n) output signal line is connected to the output control circuit 3i.
Therefore, the i-th (i=1, . . . , n) input/output part I/Oi of each of the section parts S1, . . . , Sk of the cell array Ar1 is connected to the output control circuit 3i via the i-th output signal line, and the i-th (i=1, . . . , n) input/output part I/Oi of each of the section parts S1, . . . , Sk of the cell array Ar2 is connected to the output control circuit 3n+i via the (n+i)-th output signal line. The output of the output control circuit 3i (i=1, . . . , 2n) is fed to a corresponding output Tr circuit 5i.
In the semiconductor memory device shown in FIG. 5, the total wiring capacity of the respective output signal lines is constant with respect to any one of the section parts or any one of the input/output parts.
The construction of another conventional semiconductor memory device having the layout of the memory cell array shown in FIG. 4 is shown in FIG. 6. In this semiconductor memory device, an additional signal Ad is newly introduced into the semiconductor memory device shown in FIG. 5, to select a cell array Ar1 by the additional signal Ad and to select a cell array Ar2 by the additional signal /Ad which is the inverted signal of the additional signal Ad. In addition, n selecting circuits 41, . . . , 4n are newly provided between 2n output control circuits 31, . . . , 32n and n output Tr circuits 51, . . . , 5n.
The selecting circuit 4i (i=1, . . . , n) is designed to select the output of the output control circuit 3i or the output of the output control circuit 3n+i on the basis of the additional signal Ad to transmit the selected output to a corresponding output Tr circuit 5i.
With this construction, assuming that the word length of the semiconductor memory device shown in FIG. 5 is WL, the semiconductor memory device shown in FIG. 6 is a product having a bit configuration of 2WLxc3x97n. Furthermore, the semiconductor memory device shown in FIG. 5 is a product having a bit configuration of WLxc3x972n.
The conventional semiconductor memory device shown in FIG. 6 uses half (=n/2) the n output transistor circuits on the side of the cell array Ar1, and does not use the remaining half the output transistor circuits, although this depends on the pin arrangement of the package. This is the same with respect to the n output transistor circuits on the side of the cell array Ar2. That is, the semiconductor memory device uses half the n output transistor circuits 51, . . . , 5n in FIG. 5, e.g., the output transistor circuits 51, . . . , 5n/2, as the output transistor circuits of the cell array Ar1 of FIG. 6, and uses half the n output transistor circuits 5n+1, . . . , 52n, e.g., the output transistor circuits 5n+1, . . . , 53n/2, while it does not use the other transistor circuits.
Since the layout shown in FIG. 4 is used when the semiconductor memory device shown in FIG. 6 is produced by changing an AL wiring such as an AL master slice, it is required to newly draw an output line 15 of each of the output control circuits 3i (i=1, . . . , 2n) as shown in FIG. 6.
For that reason, in the conventional semiconductor memory device shown in FIG. 6, the characteristics of access time are deteriorated by the delay time of the wiring 15 in comparison with the construction of the semiconductor memory device shown in FIG. 5. This deterioration of the characteristics of access time is more remarkable as the capacity of the memory device increases since the length of the drawn wiring increases.
The construction of a further conventional semiconductor memory device having the layout of the memory cell shown in FIG. 4 is shown in FIG. 7. In this semiconductor memory device, an additional signal Ad is newly introduced into the semiconductor memory device shown in FIG. 5, to select a cell array Ar1 by the additional signal Ad and to select a cell array Ar2 by an additional signal /Ad. The i-th (i=1, . . . , n) input/output part I/Oi of each of k section parts S1, . . . , Sk of the cell array Ar1 is connected to an output selecting circuit 2i via the first output signal line, and the i-th (i=1, . . . , n) input/output part I/Oi of each of k section parts S1, . . . , Sk of the cell array Ar2 is connected to the output selecting circuit 2i via the (n+i)-th output signal line.
Each of the output selecting circuits 2i (i=1, . . . , n) is designed to select the output of the cell array Ar2, which is transmitted via the i-th output signal line, or the output of the cell array Ar2 which is transmitted via the (n+i)-th output line, on the basis of the additional signal Ad to transmit the selected output to a corresponding output transistor 5i.
The semiconductor memory device shown in FIG. 7 has output control circuits 21, . . . , 2n, and output transistor circuits 51, . . . , 5n. The semiconductor memory device shown in FIG. 7 is a product having a bit configuration of 2WLxc3x97n similar to the semiconductor memory device shown in FIG. 6.
However, in the semiconductor memory device shown in FIG. 7, it is required to draw an output signal line 16 from the side of the cell array Ar2 to the output selection control circuits 21, . . . , 2n as shown in FIG. 7, so that the length of the output signal line is longer than that of the conventional semiconductor memory device shown in FIG. 5. For that reason, the characteristics of access time are deteriorated similar to the semiconductor memory device shown in FIG. 6.
In order to prevent such deterioration of the characteristics of access time, a semiconductor memory device shown in FIG. 8 is considered. The semiconductor memory device shown in FIG. 8 is constructed so as to obtain a product having a bit configuration of 2xc2x7WLxc3x97n by introducing an additional signal Ad. In this semiconductor memory device, the (2ixe2x88x921)-th (i=1, . . . , n/2) input/output part of each of k section parts S1, . . . , Sk of a cell array Ar1 is connected to an output selection control circuit 2i via the (2ixe2x88x921)-th output signal line, and the 2i-th input/output part is connected to the output selection control circuit 2i via the 2i-th output signal line. In addition, the (2ixe2x88x921)-th (i=1, . . . , n/2) input/output part of each of k section parts S1, . . . , Sk of a cell array Ar2 is connected to an output selection control circuit 2n/2+i via the (n/2+2i)-th output signal line, and the 2i-th input/output part is connected to the output selection control circuit 2n/2+i via the (n/2+2I)-th output signal line.
In each of the output selection control circuits 2i (i=1, . . . , n), any one of the inputs is selected on the basis of the additional signal Ad or an additional signal /Ad, and the selected input is transmitted to a corresponding output transistor 5i. 
This semiconductor memory device has output selection control circuits 21, . . . , 2n, and output transistor circuits 51, . . . , 5n.
Therefore, in the semiconductor memory device shown in FIG. 8, each of the section parts Si (i=1, . . . , k) has two input/output part I/Om connected to the same output selection control circuit 2m (m=1, . . . , n/2) as shown in FIG. 9. It is determined by the additional signal Ad or additional signal /Ad which of the two input/output parts I/Om is selected.
While the section part S1 of the cell array Ar1 has been shown in FIG. 9 for simple explanation, this is the same with respect to other section parts.
In the semiconductor memory device shown in FIG. 8, the length of the output signal line is the same as that of the semiconductor memory device shown in FIG. 5, so that it is possible to inhibit the characteristics of access time from deteriorating.
However, as can be clearly seen from the above description, this is effective if only the number n of input/output parts I/On of one section part is even, and it is not effective when the number n is odd.
When the number n is odd, one input/output part, which is not selected by a set of an additional signal Ad and an additional signal /Ad, exists in each of the section parts Si (i=1, . . . , k) of the cell array Ar1 as shown in FIG. 10. In addition, as shown in FIG. 11, one input/output part, which is not selected by a set of an additional signal Ad and an additional signal /Ad, exists in each of the section parts Si (i=1, . . . , k) of the cell array Ar2.
For that reason, as shown in FIG. 12, in the semiconductor memory device when the number n is odd, the input/output parts must be arranged so as to extend over the cell arrays Ar1 and Ar2, so that it is required to draw an output signal line 20 only with respect to a specific one input/output part. Thus, the characteristics of access time in the specific input/output part (the input/output part I/O(n+1)2 in FIG. 12) are deteriorated.
It is well known that the number of input/output parts of each of cell arrays is odd in actual semiconductor memory device. Referring to FIGS. 13 and 14, this will be described below.
FIG. 13 is a plan view of a package having four sets of I/O pin groups, each of which has odd I/O pins. FIG. 14 is a layout drawing showing the construction of a chip for use in the package shown in FIG. 13. Four memory cell arrays MAr1, . . . , MAr4 exist substantially at the central portion of a chip 100 for use in this package, and pad groups 301, 302, 303 and 304, each of which comprises odd pads, are provided in the vicinity of the respective memory cell arrays. Each of the pad groups 30i (i=1, . . . , 4) is connected to the I/O pin group 40 shown in FIG. 13 by means of a wire bonding or the like, and connected to the memory cell array MAri. Therefore, each of the section parts S1, . . . , Sk constructing the memory cell array MAri (i=1, . . . , 4) has odd input/output parts.
It is therefore an object of the present invention to eliminate the aforementioned problems and to provide a semiconductor memory device capable of preventing access characteristics from deteriorating between output signal lines.
In order to accomplish the aforementioned and other objects, according to one aspect of the present invention, a semiconductor memory device comprises: first and second cell arrays, each of which has the same number of memory cells; first through (2nxe2x88x921)-th (nxe2x89xa71) output selection control circuits; first through (2nxe2x88x921)-th output transistor circuits which are provided so as to correspond to the first through (2nxe2x88x921)-th output selection control circuits, and each of which receives the output of a corresponding one of the output transistor circuits; and first through (4nxe2x88x922)-th output signal lines, each of the first and second cell arrays being divided into k (kxe2x89xa72) first through k-th section parts, each of which has 2nxe2x88x921 first through (2nxe2x88x921)-th output parts and at least one auxiliary input/output part, the i-th (i=1, . . . , nxe2x88x921) output selection control part receiving the output of the (2ixe2x88x921)-th input/output part of each of the first through k-th section parts of the first cell array via the (2ixe2x88x921)-th output signal line and receiving the output of the 2i-th input/output part of each of the first through k-th section parts of the first cell array via the 2i-th output signal line, the n-th output selection control part receiving the output of the (2nxe2x88x921)-th input/output part of each of the first through k-th section parts of the first cell array via the (2nxe2x88x921)-th output signal line and receiving the output of the auxiliary input/output part of each of the section parts of the first cell array via the 2n-th output signal line, and the (n+i)-th (i=1, . . . , nxe2x88x921) output control circuit receiving the output of the (2ixe2x88x921)-th input/output part of each of the first through k-th section parts of the second cell array via the (2n+2ixe2x88x921)-th output signal line and receiving the output of the 2i-th input/output part of each of the first through k-th section parts of the second cell array via the (2n+2i)-th output signal line.
Preferably, the first through (2nxe2x88x921)-th output selection control circuits selects one of two input signals on the basis of an additional signal, and transmits the selected signal to a corresponding one of the output transistor circuits.